MOSFET current mirror and active-load amplifier: what a gain of hundreds costs

A PMOS current mirror as a current source, then as the load of a common-source amplifier: operating point, gain, power, and what goes wrong on a breadboard, from PSpice results.

A common-source amplifier with a resistor load (MOSFET amplifier guide) gets a gain of a few, set by R_D. Swap the resistor for a current source and the load's small-signal resistance becomes huge, so the gain climbs into the hundreds. The numbers here are PSpice results for the lab handout's circuits (IRF510, IRF4905) and values calculated from them, not measurements.

1. The circuit

2. How a current mirror works

M_p2, with gate tied to drain, is always in saturation and makes whatever V_SG its current needs. M_p1 shares its gate and source, so it gets the same V_SG and, while it stays in saturation, passes the same current. The difference comes from channel-length modulation (λ) when the two V_SD differ, plus part-to-part spread.

3. Current source: changing R_ref (V_DD 10 V)

• V_SG hardly moves: taking I_o = I_ref and V_SG = V_DD − |I_o|R_ref, it shifts only 59 mV while the current changes 9.9 times. So the output current is practically (V_DD − V_SG)/R_ref, and the formula column matches PSpice closely. This IRF4905 model has a very large K, so everything from a few mA to tens of mA flows just above threshold.
• Negative currents in PSpice: PSpice measures current into the device pin. Compare magnitudes.
• A small R_ref means heat: at R_ref = 100 Ω the resistor dissipates about 0.44 W, too much for a ¼ W part. The output transistor M_p1, with its drain grounded, takes the full 10 V of V_SD and dissipates 0.66 W.
• A real part's V_SG differs: the IRF4905 datasheet spreads V_GS(th) from −2 to −4 V. The output current goes with V_DD − V_SG, so the lower V_DD, the more that spread shows. The two PMOS parts can differ too: pick them from the same batch and record both I_ref and I_o.

4. The active-load common-source amplifier (V_DD 20 V, R_ref 100 Ω)

The gate divider R₁ = 390 kΩ, R₂ = 105 kΩ gives V_G = 4.242 V, which with the source grounded is V_GS (PSpice 4.24 V). PSpice put the operating point at I_DQ = 168.8 mA, V_DSQ = 10.05 V, and a 10 mV-amplitude (20 mV_p-p), 10 kHz input came out inverted at 7.572 V_p-p.

• Gain: 7.572 ÷ 0.02 ≈ 379 V/V (about 51.6 dB), roughly a hundred times a resistor-loaded common-source stage.
• The mirror sets the bias current: if V_SG is about what it was in section 3, I_ref ≈ (20 − 3.35) ÷ 100 ≈ 166 mA, and PSpice's I_DQ is close to it. M_p1 has more V_SD than M_p2 (the λ effect), so it passes slightly more.

The last line says the gain barely depends on how much current flows; it is set by the overdrive voltage and the two devices' λ. Cutting the current at the same V_GS − V_th leaves the gain alone, and cutting it while lowering the overdrive actually raises it.

5. What goes wrong on a breadboard

The operating point slams into a rail

There is no capacitor at the drain, so DC changes at the gate reach the output with the same gain. With 9.95 V of headroom above and 10.05 V below, the gate only has to be off by about 26 mV for the output to stick to the supply rail or 0 V. Yet with 5% resistors pulling opposite ways, V_G can move by up to about 325 mV, and by 66 mV even with 1% parts. The part's V_th spread (IRF510 datasheet: 2 to 4 V) is far larger still. Built with the handout's values as they are, the output DC almost certainly ends up pinned at one end.

• Put a multi-turn trimmer on the R₁ or R₂ side and slowly bring the drain's DC voltage to about half of V_DD while watching it.
• Even after that, the threshold falls as the part warms (typically a few mV per °C) and the output wanders. Wait a few minutes, trim again and measure right away.

Heat: several watts with the handout's values

Without a heat sink the IRF510's junction-to-ambient thermal resistance is about 62 °C/W, so 1.7 W heats it roughly 105 °C above the room. R_ref = 100 Ω needs a resistor rated 2 W or more. On a breadboard it is safer to fit a heat sink, or raise R_ref to bring the current down to a few mA or tens of mA (as section 4 shows, the gain does not drop much) and re-pick the gate divider for that current. Set the supply's current limit as well.

Making a 20 mV_p-p input

• Near a function generator's minimum amplitude, noise and offset are relatively large. Generate about 1 V_p-p and divide it down with resistors (say 10 kΩ and 200 Ω, about 1/51) for a cleaner signal.
• The input capacitor C = 10 µF with R₁‖R₂ ≈ 82.7 kΩ has a time constant of about 0.83 s. Wait a few seconds after power-up or after re-trimming the bias.
• If only one side of the output is flattened, the operating point is close to that rail. Check the drain's DC voltage before turning the input down.
• For the input, a 1× probe or the scope's bandwidth limit plus Average mode makes mV signals readable. Work out the gain from the signal actually reaching the gate side, after the divider.

6. In your lab report

• In the current-source table, record I_ref (or V_SG) next to I_o so the mirror ratio I_o/I_ref can be read off.
• For the amplifier, record the drain's DC voltage at the time alongside the gain. The same circuit gives very different gain and maximum output depending on where it is biased.
• The simulation models' λ and V_th (IRF510, IRF4905) differing from the real parts is a fair cause to discuss for any gap.

Check part temperatures with the heat sink calculator, turn the gain into dB with the dB calculator, and resistor power with the Ohm's law calculator.