MOSFET common-source and common-drain amplifiers: gain formulas, PSpice and the threshold voltage

The operating point, g_m and voltage gain of 2N7000 common-source and common-drain amplifiers, PSpice against the formulas, and what the part's threshold does to the circuit.

A MOSFET amplifier rides a small AC signal on the operating point set up in the bias lab and makes it bigger. The circuit numbers here are PSpice results for the lab handout's circuits with a 2N7000 model (V_th 2.1 V), and values calculated from them. They are not measurements; where a real part's threshold is used, it says so.

1. The small-signal model and the gain formulas

In saturation I_D = K(V_GS − V_th)², so the rate at which the current changes for a small change in V_GS at the operating point (the transconductance) is as below. For the same current, a smaller V_GS − V_th (overdrive) means a larger g_m.

Common source inverts (180°); common drain keeps the phase with a gain just under 1. Both formulas assume the bias resistors (R₁‖R₂) are far larger than the source resistance and that the output resistance r_d can be ignored.

2. The circuit

3. Common source: the operating point

V_DD = 10 V, R₁ = 430 kΩ, R₂ = 160 kΩ, R_D = 4.7 kΩ, R_S = 470 Ω. The divider gives V_G = 2.712 V and PSpice reports 2.71 V. The PSpice operating point is I_DQ = 939 µA, V_DSQ = 5.15 V, g_m = 10.99 mA/V.

• Check it with KVL: V_DD − I_DQ(R_D + R_S) = 5.15 V, the same as PSpice's V_DSQ.
• V_GS backwards from g_m: solving g_m = 2I_DQ/(V_GSQ − V_th) gives V_GSQ ≈ 2.271 V, an overdrive of 0.171 V. V_DSQ is far above that, so the point sits well inside saturation.

4. Common source: the voltage gain

PSpice with 1 V_p-p in at 1 kHz and only the load R_L changing, against the two formulas:

• The estimate runs 22% high: this circuit's g_mR_S is 5.17, too small to call '≫ 1'. The estimate inflates the real gain by 1 + 1/(g_mR_S) = 1.19.
• The formula with g_m is within 2% of PSpice: what remains is the ignored output resistance r_d, plus a signal large enough that the straight-line approximation around the operating point starts to slip.
• R_S costs gain and buys stability: bypass R_S with a capacitor and the gain becomes −g_m(R_D‖R_L) = −21.3 (R_L 3.3 kΩ), but it is then proportional to g_m and drifts with the part and temperature.
• Is the input too big? Of the 0.5 V input peak only about 81 mV lands across gate and source, roughly half the 171 mV overdrive. As that ratio grows, the square law gives the two half cycles different gains and the waveform turns lopsided.

5. Common drain (source follower)

V_DD = 10 V, R₁ = 390 kΩ, R₂ = 680 kΩ, R_S = 1.8 kΩ. The divider gives V_G = 6.355 V; the PSpice operating point is V_SQ = 3.993 V, I_DQ = 2.22 mA, g_m = 16.90 mA/V.

• Gain: the formula gives 0.968; PSpice gives 5.79 V_p-p ÷ 6 V_p-p = 0.965, practically the same. With g_mR_S = 30.4 it is close to 1.
• Why it is a buffer: input resistance R₁‖R₂ ≈ 248 kΩ, output resistance R_S‖(1/g_m) ≈ 57 Ω. A load hardly dents the gain:

  RL	RS‖RL	Av	Output p-p (6 V in)
  none	1.8 kΩ	0.968	5.81 V
  10 kΩ	1.53 kΩ	0.963	5.78 V
  1 kΩ	643 Ω	0.916	5.49 V
  100 Ω	94.7 Ω	0.616	3.69 V

• When does it clip? If the output swings down by more than V_SQ = 3.993 V the source reaches 0 V and the MOSFET turns off. At a gain of 0.965 that allows about 8.3 V_p-p in.

6. Design: gain −10 at I_DQ = 1 mA

An example on V_DD = 15 V with V_G = 3 V (R₁ = 4R₂, R₂ = 150 kΩ), designed for a part with K = 180 mA/V² and V_th = 2.1 V.

Standard values pull V_G down to 2.922 V, so I_DQ lands below target. Worked out with the same part, 916 µA matches PSpice's 916 µA, and with g_mR_S = 21.1 the gain comes to −9.55, 95% of the −10 estimate. Setting gain by a resistor ratio only works when g_mR_S is large, and the numbers show it.

7. With a real part: the DC point first

The 2N7000 actually measured in the I–V lab had V_th ≈ 1.53 V, more than 0.5 V below the model's 2.1 V. Suppose the same part goes into these circuits:

• The lab 11-1 circuit falls into triode: in PSpice (V_th 2.1 V), V_DSQ was 5.15 V; with 1.53 V, I_D ≈ 1.93 mA and V_DSQ ≈ 0.03 V, in triode. Put a signal in and almost nothing comes out.
• The design circuit is on the edge too: V_DSQ drops to about 0.98 V, so even a small output swing clips at the bottom.
• So DC before signal: before connecting the function generator, read V_G, V_S and V_D with a multimeter and check V_DS > V_GS − V_th. If it is in triode, lower V_G (smaller R₂) or add a trimmer on the R₁ side to bring V_DSQ near half of V_DD, then add the signal.

8. Common measurement mistakes

• Don't measure right after power-up: C_C1 = 100 µF charges through R₁‖R₂ with a time constant of about 12 s. The gate's DC level takes close to a minute to settle, and gain or bias readings taken before then keep moving.
• Electrolytic polarity: C_C1 goes + towards the gate (DC 2.7 V), C_C2 + towards the drain (several volts DC).
• Function generator load setting: if the output is set for a 50 Ω load, a high-impedance circuit gets twice the displayed amplitude. Measure v_s on the scope rather than trusting the display.
• AC-couple the output, compare phase on two channels: the common-source inversion (180°) only shows with both channels on the same timebase. The common-drain output rides on the source's 4.0 V DC, so with DC coupling you need to adjust the vertical position.
• Gain as a peak-to-peak ratio: use the scope's V_pp measurement, and Average mode to tame noise on small signals.

9. In your lab report

• Put the estimate, the formula with g_m, and PSpice (or the bench) in one table with g_mR_S beside them; the reason for the differences is then obvious.
• Take g_m from the operating point's I_DQ and V_GSQ − V_th. On the bench, use the V_th you measured on your own part rather than the handout's, and say which you used.
• Rather than just writing 'inverted', attach a screen with both waveforms as the evidence.

Check the gate divider with the voltage divider calculator and turn gains into dB with the dB calculator. The same circuits built with a BJT are in the BJT amplifier guide.