Two's Complement Calculator
See step by step how a negative number becomes two's complement, and find the signed value of any bit pattern.
The binary field uses the number of digits you type as its width, so 1011 is read as 4 bits.
How to form two's complement
For −n, write n in binary, invert every bit and add 1. This lets an adder do subtraction, which is why CPUs and ALUs use it. N bits cover −2N−1 to 2N−1−1.
Worked example: −5 in 8-bit two's complement
- Write the magnitude 5 in 8 bits: 0000 0101
- Invert every bit: 1111 1010
- Add 1: 1111 1011 = 0xFB
- Check: 1111 1011 + 0000 0101 = 1 0000 0000 → drop the carry and you get 0
4-bit two's complement table
| Bit pattern | Unsigned | Two's complement |
|---|---|---|
| 0000 | 0 | 0 |
| 0001 | 1 | +1 |
| 0010 | 2 | +2 |
| 0011 | 3 | +3 |
| 0100 | 4 | +4 |
| 0101 | 5 | +5 |
| 0110 | 6 | +6 |
| 0111 | 7 | +7 |
| 1000 | 8 | −8 |
| 1001 | 9 | −7 |
| 1010 | 10 | −6 |
| 1011 | 11 | −5 |
| 1100 | 12 | −4 |
| 1101 | 13 | −3 |
| 1110 | 14 | −2 |
| 1111 | 15 | −1 |
Range by number of bits
| Bits | Signed range | Unsigned range |
|---|---|---|
| Bits4 | Signed range−8 ~ 7 | Unsigned range0 ~ 15 |
| Bits8 | Signed range−128 ~ 127 | Unsigned range0 ~ 255 |
| Bits16 | Signed range−32,768 ~ 32,767 | Unsigned range0 ~ 65,535 |
| Bits32 | Signed range−2,147,483,648 ~ 2,147,483,647 | Unsigned range0 ~ 4,294,967,295 |
Using it in practice
Step by step
- Choose the word size (4, 8, 16 or 32 bits); the same number looks different in each.
- Enter a signed decimal value, or a binary or hex pattern to decode.
- Follow the steps shown: invert the bits of the magnitude, then add one.
Common mistakes
- Going outside the range. n bits hold −2^(n−1) to 2^(n−1) − 1, so 8 bits cover −128 to 127. +128 does not fit in a signed byte.
- Padding with zeros when widening. To extend a negative number to more bits, copy the sign bit: −3 is 1101 in 4 bits and 1111 1101 in 8 bits, not 0000 1101.
- Missing overflow. Adding two positives that gives a negative result (or two negatives giving a positive) means overflow, even though no carry warning appears in the bits.
Why computers use it
With two's complement, the same adder circuit handles signed and unsigned numbers, and subtraction is just adding the complement. There is only one zero, unlike sign-magnitude. The cost is one odd value: the most negative number (−128 in 8 bits) has no positive partner, so negating it gives itself back. The 4-bit ALU simulator shows the carry and overflow flags for the same additions.
Worked example: decoding a signed sensor register
Many temperature sensors return a 16-bit two's complement value. Suppose the register reads 0xFF38. As an unsigned number that is 65,336; the top bit is 1, so subtract 216 = 65,536 to get −200. If the datasheet says one count is 0.0625 °C, the temperature is −200 × 0.0625 = −12.5 °C.
The same rule works at any width. An 8-bit ADC offset register holding 0xC4 is 196 unsigned, and 196 − 256 = −60. The usual bug is reading such a register into a wider unsigned variable without sign extension, which turns −60 into +196.
Overflow you can see in four bits
- 4 bits hold −8 to 7: 0111 is 7, 0001 is 1, 0000 is 0, 1111 is −1 and 1000 is −8.
- 5 + 4: 0101 + 0100 = 1001. The bits are right for unsigned 9, but as a signed number 1001 is −7. Two positives gave a negative, so the result overflowed.
- −3 + −2: 1101 + 1110 = 1 1011. Drop the carry and 1011 is −5, the correct answer. A carry out of the top bit is normal here and is not overflow.
The quick test is the sign rule: overflow can only happen when both operands have the same sign, and it shows up as a result with the other sign. The 4-bit ALU simulator computes the same flags.
Frequently asked questions
What is −1 in 8-bit two's complement?
1111 1111 (0xFF). Write 1 as 0000 0001, invert it to 1111 1110 and add 1.
How can I tell if a two's complement number is negative?
Look at the leftmost bit. If it is 1, the number is negative, and its value is the unsigned value minus 2 to the power of the bit width.