Lab guide
Building AND, OR and NOT from NAND or NOR gates (measured)
Output voltages of gates built from a 7400 and a 7402, checked against logic level limits.
NAND and NOR are "universal" gates: either one alone can make AND, OR and NOT. These are real measurements from circuits built with a 7400 (NAND) and a 7402 (NOR), switching the inputs between 0 V and 5 V and reading the output on a multimeter.
1. How to wire them
| Built from | Gate | Wiring | Gates |
|---|---|---|---|
| NAND | NOT | NAND(A, A) | 1 |
| NAND | AND | NAND(NAND(A, B), NAND(A, B)) | 2 |
| NAND | OR | NAND(NAND(A, A), NAND(B, B)) | 3 |
| NOR | NOT | NOR(A, A) | 1 |
| NOR | OR | NOR(NOR(A, B), NOR(A, B)) | 2 |
| NOR | AND | NOR(NOR(A, A), NOR(B, B)) | 3 |
Every wiring in the table is checked in code against all four input combinations. AND is simplest from NAND and OR is simplest from NOR, at two gates each; the other way round takes three.
2. Measurements
| Circuit | Input | Measured output | Expected | Match |
|---|---|---|---|---|
| NAND → AND | 00 | −1.68 mV | 0 | ✓ |
| NAND → AND | 01 | 0.01 mV | 0 | ✓ |
| NAND → AND | 10 | 0.01 mV | 0 | ✓ |
| NAND → AND | 11 | 4.9774 V | 1 | ✓ |
| NAND → OR | 00 | 0.11 mV | 0 | ✓ |
| NAND → OR | 01 | 4.9956 V | 1 | ✓ |
| NAND → OR | 10 | 4.9590 V | 1 | ✓ |
| NAND → OR | 11 | 4.9873 V | 1 | ✓ |
| NAND → NOT | 0 | 4.9254 V | 1 | ✓ |
| NAND → NOT | 1 | 0.00 mV | 0 | ✓ |
| NOR → AND | 00 | −0.16 mV | 0 | ✓ |
| NOR → AND | 01 | 0.12 mV | 0 | ✓ |
| NOR → AND | 10 | −0.28 mV | 0 | ✓ |
| NOR → AND | 11 | 4.9557 V | 1 | ✓ |
| NOR → OR | 00 | 9.96 mV | 0 | ✓ |
| NOR → OR | 01 | 4.8822 V | 1 | ✓ |
| NOR → OR | 10 | 4.8852 V | 1 | ✓ |
| NOR → OR | 11 | 4.8847 V | 1 | ✓ |
| NOR → NOT | 0 | 4.9125 V | 1 | ✓ |
| NOR → NOT | 1 | 9.75 mV | 0 | ✓ |
Reading anything at or below 0.8 V as 0 and at or above 2.0 V as 1 (74LS limits), all 20 readings match. High outputs were 4.88 to 5.00 V and Low outputs −1.68 mV to 9.96 mV, far inside the output limits (High ≥ 2.7 V, Low ≤ 0.5 V). Nothing else was connected to the outputs, so the values are close to ideal.
3. Switching threshold
Driving the input with a slowly changing voltage and overlaying input and output on an oscilloscope, the output switched at about 1.5 V. That has to lie between the Low limit of 0.8 V and the High limit of 2.0 V, and it does. The datasheet leaves this band undefined because the threshold varies a little from chip to chip and with temperature.
4. When a square wave looks tilted on the scope
During the lab the square wave input looked tilted instead of flat. The usual cause is the channel being set to AC coupling. AC coupling is a high-pass filter that blocks DC, so the flat tops sag toward 0 V over time. Assuming a 10 Hz coupling corner, the sag is:
| Square wave frequency | Sag over each half-cycle |
|---|---|
| 50 Hz | 46.7% |
| 100 Hz | 27.0% |
| 500 Hz | 6.1% |
| 1 kHz | 3.1% |
| 10 kHz | 0.3% |
Logic waveforms depend on their DC level, so switch the channel to DC coupling. A probe that is out of compensation (adjusted with the screw while touching the scope's calibration terminal) also makes the corners look rounded or spiky.
5. In your lab report
- State which limits you used to turn voltages into 0 and 1, for example 0.8 V and 2.0 V for 74LS.
- If you changed inputs by plugging jumpers in and out rather than with switches, make sure a 0 input went to GND rather than being left floating.
For multi-bit circuits, get the expected values first with the number base converter and the 4-bit ALU calculator.